1. Field of the Invention
The present invention relates to a data recovery circuit, and more particularly, to a circuit and a method for minimizing a phase error of a sampling clock in a data recovery circuit.
2. Description of the Related Art
DVI (Digital Visual Interface) is a digital display interface standard established by several PC and graphic card manufacturers. Thanks to the high speed and the excellent display quality of the DVI transmission system, it is foreseeable that DVI interface will become a widely used standard interface for image display in the near future.
FIG. 1 illustrates the data transmission structure of a display system configured with DVI standard. The system mainly comprises a host portion 10 and a display portion 20. In the host portion 10, a graphic card 12 is used to generate three 8-bit digital image signals R[0:7], G[0:7], and B [0:7] respectively for the three primary colors of red, green and blue. According to DVI standard, these 8-bit digital image signals are then sent to a DVI encoder 14 to be encoded into 10-bit DVI image signals R′[0:9], G′[0:9] and B′[0:9], which are subsequently converted by a DVI transmitter 16 into differential serial image signals [R+:R−], [G+:G−] and [B+:B−] and transmitted by a DVI transmission cable 18 to the display portion 20. Note that the three differential serial image signals [R+:R−], [G+:G−] and [B+:B−] should be transmitted respectively by three pairs of differential transmission lines. Moreover, these differential serial image signals should be transmitted at a frequency equal to ten times the rate of the 10-bit DVI image signals since they are generated from the 10-bit signals by a parallel-to-serial conversion. However, a differential clock signal [CK+:CK−] generated by the DVI transmitter 16 is transmitted at the original rate. For simplicity, all the differential transmission lines are represented by only one DVI transmission cable 18 in FIG. 1. A DVI receiver 22 in the display portion 20 is used for receiving the differential image signals and for recovering 10-bit DVI image signals from those differential image signals. Thereafter, the recovered 10-bit DVI image signals are decoded by a DVI decoder 24 into 8-bit digital image signals for display on a display panel (not shown in the drawings).
In order to recover 10-bit DVI image signals, the DVI receiver 22 is typically provided with a data recovery circuit for obtaining recovered data signals by taking samples of the differential image signals in accordance with a sampling clock generated from the received differential clock signal. A conventional serial data sampling technique is shown in FIG. 3(a), in which a clock signal 32 having a frequency equal to the rate of the incoming data 30 is generated to sample the incoming data 30. Each of the rising edges of the clock signal 32 is approximated aligned to a central portion 36 of one data bit in the incoming data 30 to ensure correct sampling of the data.
FIGS. 3(a) and 3(b) illustrate conventional serial data sampling scheme, in which FIG. 3(a) shows the condition without clock skew and FIG. 3(b) shows the condition with clock skew;
However, according to the DVI standard, the differential image signal is transmitted at an extremely high rate, for example, at several giga-hertz (GHz), and it is very difficult to generate a sampling clock with such a high frequency. Furthermore, in a data transmission high up to several giga-hertz, the transmitted signals are vulnerable to jitters and high-frequency reflective interferences, which significantly reduces the effective period for valid sampling of a data bit. As can be seen in FIG. 2, due to the reflective interferences 28a, the effective sampling period of a data bit 28 is reduced from T to about T/2. Therefore, if there is a significant skew between a sampling edge 38 of the sampling clock and a central portion 36 of a data bit in the incoming data 30, i.e., the condition that the sampling clock 34 is out of phase with the incoming data 30, as shown in FIG. 3(b), then it is very possible to obtain an incorrect sampling data.
Accordingly, there is a need to develop a data recovery circuit, which is suitable for applications of high frequency serial data transmission, and in which a sampling clock with lower frequency can be used for sampling the high frequency serial data while the sampling edges of the sampling clock are always maintained in positions aligned with the central portions of the data bits.